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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-03-28 19:48:42 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-06 06:43:43 +0000 |
| commit | d85c4afea56b3ca0eca4de3707884802bbdcca45 (patch) | |
| tree | 543df0e77bc5c8457a352601996d187052fcec55 /src/soc/amd/stoneyridge/bootblock | |
| parent | 3f42a26b421555dae88bbeae46b7de8835d4e2bd (diff) | |
| download | coreboot-d85c4afea56b3ca0eca4de3707884802bbdcca45.tar.xz | |
amd/stoneyridge: Use defined value for SPI flash MTRR
Replace an absolute value with a #define value in bootblock. This is
in preparation for using an additional MTRR in a subsequent patch.
Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/bootblock')
| -rw-r--r-- | src/soc/amd/stoneyridge/bootblock/bootblock.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index fafaf079ce..db5c9b62b9 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -25,6 +25,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> #include <soc/pci_devs.h> +#include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> @@ -61,7 +62,7 @@ static void amd_initmmio(void) * todo: AGESA currently writes variable MTRRs. Once that is * corrected, un-hardcode this MTRR. */ - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2; + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH; set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); } |