soc/amd/stoneyridge/gpio.c: Create I2C slave reset code

AMD's SOC do not wait for I2C transactions to complete before executing
a reset. Because of this, it's possible for the reset to happen in the
middle of a transaction, resulting on a slave hang. There are 2 possible
solutions:
If the slave has a reset pin connected to a GPIO pin, it can be used to
reset the slave, else the only solution is to bang SCL 9 times. Create
code that makes it easy to implement SCL bang, using a devicetree
register to define which I2C SCL lines needs to be reset.

BUG=b:114479395
TEST=Build and boot grunt. Look at transactions on a scope.

Change-Id: I7f74b7e45c509044825355874753969f074e2382
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28574
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 9 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index 4cf2b33596..8ed8e4d903 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -50,6 +50,15 @@ struct soc_amd_stoneyridge_config {
 	/* Used if UMAMODE_SPECIFIED_SIZE is set. */
 	size_t uma_size;
 
+	/*
+	 * If sb_reset_i2c_slaves() is called, this devicetree register
+	 * defines which I2C SCL will be toggled 9 times at 100 KHz.
+	 * For example, should we need I2C0 and  I2C3 have their slave
+	 * devices reseted by toggling SCL, use:
+	 *
+	 * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
+	 */
+	u8 i2c_scl_reset;
 	struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX];
 	u8 stapm_percent;
 	u32 stapm_time;