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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-06-15 12:17:38 -0600
committerMartin Roth <martinroth@google.com>2017-06-27 20:50:54 +0000
commit4e101ada37c10282030729f4a03fd505bd4f526d (patch)
tree7cdb6f41b198ef1e9c30f66da854572893de91ed /src/soc/amd/stoneyridge/chip.h
parent4692e2fc95605a997cd9cd1cdb711e6c1f6869bc (diff)
downloadcoreboot-4e101ada37c10282030729f4a03fd505bd4f526d.tar.xz
soc/amd/stoneyridge: Fix most checkpatch errors
Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/chip.h')
-rw-r--r--src/soc/amd/stoneyridge/chip.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index f913b055a2..747c2956f1 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -18,8 +18,7 @@
#include <stdint.h>
-struct soc_amd_stoneyridge_config
-{
+struct soc_amd_stoneyridge_config {
u8 spdAddrLookup[1][1][2];
u32 ide0_enable : 1;
u32 sata0_enable : 1;