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| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2019-06-28 09:18:47 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-31 09:11:05 +0000 |
| commit | 9247e86f288fadf2fcff4b61a64f05cbf6e60b1e (patch) | |
| tree | cb433b52ead9ca8c50a6d62f3c796702ccb62be3 /src/soc/amd/stoneyridge/chip.h | |
| parent | cac5e9472622f43c0b33d70f20adef801b345773 (diff) | |
| download | coreboot-9247e86f288fadf2fcff4b61a64f05cbf6e60b1e.tar.xz | |
soc/amd/stoneyridge: Change code to accommodate Merlin Falcon SOC
Stoney Ridge is family 15h models 70h-7Fh, Merlin Falcon is family 15h models
60h-6Fh. Add changes based on config parameter SOC_AMD_MERLINFALCON to make
the code backward compatible with Merlin Falcon.
BUG=none.
TEST=Tested later with padmelon board.
Change-Id: I00fe832324500bcb07fca292a0a55f7258a2d82f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33624
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/chip.h')
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index d1a7d30199..00b675cbb0 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -23,9 +23,15 @@ #include <soc/i2c.h> #include <arch/acpi_device.h> +/* Merlin Falcon supports 2 channels, Prairie Falcon only 1 (channel B) */ #define MAX_NODES 1 +#if CONFIG(SOC_AMD_MERLINFALCON) && CONFIG(HAVE_MERLINFALCON_BINARIES) +#define MAX_DRAM_CH 2 +#define MAX_DIMMS_PER_CH 2 +#else #define MAX_DRAM_CH 1 #define MAX_DIMMS_PER_CH 2 +#endif #define STONEY_I2C_DEV_MAX 4 |