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| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-03-06 03:18:34 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-06 08:03:28 +0000 |
| commit | 345d1e39629b3548e40a82ed6d3d49bdcd5b6b88 (patch) | |
| tree | 6ad87972b495f74348ea48831704ae171729f31a /src/soc/amd/stoneyridge/chip.h | |
| parent | 41328938081a38b250bbad69829bbe091abf4e6a (diff) | |
| download | coreboot-345d1e39629b3548e40a82ed6d3d49bdcd5b6b88.tar.xz | |
Revert "mainboard/google/meowth: enable PCH iSCLK"
This reverts commit 2e81f394cffc6f1993a5f004356ed35f6064fe48, as it will
have side effect that will make system shutdown failure. System will not
enter S5 sleep state, instead a global reset will be generated.
Once camera driver ACPI framework ready, isclk programing will be moved
into APCI method, in _PS3, isclk will be turned off to save power.
BUG=b.72532565
BRANH=master
TEST=Apply the changes and flash coreboot, on meowth devices, issue
"halt" in OS stage, system can shutdown successfully.
Change-Id: If35697911f97c524d9b52bdf4dae5c9ef1cc8618
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/chip.h')
0 files changed, 0 insertions, 0 deletions