diff options
| author | Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> | 2017-06-21 16:42:53 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-27 20:46:48 +0000 |
| commit | 4692e2fc95605a997cd9cd1cdb711e6c1f6869bc (patch) | |
| tree | 497ecf92fcd4f33d4e6686f374a8d19754cf3805 /src/soc/amd/stoneyridge/chip.h | |
| parent | b3f2c9ac5977ec4d4a0391a202f90a923d06895c (diff) | |
| download | coreboot-4692e2fc95605a997cd9cd1cdb711e6c1f6869bc.tar.xz | |
mainboard/google/soraka: Update VR config settings
Update Psi2Threshold, IccMax, AcLoadline, DcLoadline
VR config settings as per board design.
BUG=b:62063434
BRANCH=none
TEST=Build and boot soraka.
Change-Id: I254bbb88b82ddf278f0ec71bc98873df1d5e0d27
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Signed-off-by: G Naveen <naveen.g@intel.com>
Reviewed-on: https://review.coreboot.org/20309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/chip.h')
0 files changed, 0 insertions, 0 deletions