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author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-10-22 13:57:18 -0700 |
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committer | Martin Roth <martinroth@google.com> | 2018-10-30 16:57:53 +0000 |
commit | 41baf0c3ff8bf23a154eb6505c4e254f5bdc253b (patch) | |
tree | e643d364058d032964026e60f01eda512bbd4f6b /src/soc/amd/stoneyridge/cpu.c | |
parent | 58bf3e763297d658ed83dd35b30293dfab3e135f (diff) | |
download | coreboot-41baf0c3ff8bf23a154eb6505c4e254f5bdc253b.tar.xz |
soc/amd/stoneyridge: Remove dev_find_slot where possible
The procedure dev_find_slot has 3 main uses. To find configuration
(devicetree), to verify if a particular device is enabled at build \
time, and to get the address for PCI access while in bootblock/romstage.
The third use can be hidden by using macros defined in pci_devs.h,
making it very clear what PCI device is being accessed. replace the
temporary pointers to device used with PCI access with SOC_XXX_DEV where
XXX is the device being accessed, and remove the setting of the temporary
pointers.
BUG=b:117917136
TEST=Build grunt.
Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/cpu.c')
-rw-r--r-- | src/soc/amd/stoneyridge/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index c140fca7db..6cb59a955d 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -55,8 +55,8 @@ static void pre_mp_init(void) static int get_cpu_count(void) { - struct device *nb = dev_find_slot(0, HT_DEVFN); - return (pci_read_config16(nb, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1; + return (pci_read_config16(SOC_NB_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) + + 1; } static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |