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author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-09-04 13:11:42 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-09-07 14:51:42 +0000 |
commit | 0b4a1e220a62ec531c4850167ef000cf4715b474 (patch) | |
tree | f988d33a23de7f3af9f92c81a1a3119e6ee1b114 /src/soc/amd/stoneyridge/cpu.c | |
parent | 4b0f6fa156a9a474adb2e1e296ed990458ecdf26 (diff) | |
download | coreboot-0b4a1e220a62ec531c4850167ef000cf4715b474.tar.xz |
amd/stoneyridge: Relocate MCA error identification
Move the process of interrogating the Machine Check registers into
its own file. This rearranges source code in preparation of supporting
a Boot Error Record Table, which stoneyridge will use to report latent
MC errors to the OS.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: Ia3275e9135dc96ba4a717c9371f38843fa1e3e64
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/cpu.c')
-rw-r--r-- | src/soc/amd/stoneyridge/cpu.c | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 09543b6b15..43ee6a029f 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -117,62 +117,6 @@ void stoney_init_cpus(struct device *dev) set_warm_reset_flag(); } -static const char *const mca_bank_name[] = { - "Load-store unit", - "Instruction fetch unit", - "Combined unit", - "Reserved", - "Northbridge", - "Execution unit", - "Floating point unit" -}; - -static void check_mca(void) -{ - int i; - msr_t msr; - int num_banks; - - msr = rdmsr(MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; - - if (is_warm_reset()) { - for (i = 0 ; i < num_banks ; i++) { - if (i == 3) /* Reserved in Family 15h */ - continue; - - msr = rdmsr(MC0_STATUS + (i * 4)); - if (msr.hi || msr.lo) { - int core = cpuid_ebx(1) >> 24; - - printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", - core, i, mca_bank_name[i]); - - printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_ADDR + (i * 4)); - printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_MISC + (i * 4)); - printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_CTL + (i * 4)); - printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_CTL_MASK + i); - printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", - i, msr.hi, msr.lo); - } - } - } - - /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; - for (i = 0 ; i < num_banks ; i++) - wrmsr(MC0_STATUS + (i * 4), msr); -} - static void model_15_init(struct device *dev) { check_mca(); |