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authorMarc Jones <marcj303@gmail.com>2017-05-15 18:55:11 -0600
committerMartin Roth <martinroth@google.com>2017-06-26 00:46:18 +0000
commit1587dc8a2b4ddfe110cd0239c6506a320cccac96 (patch)
treeab9b3b3ae63461e9fa8caf4c3fe4410f78f664c3 /src/soc/amd/stoneyridge/dimmSpd.c
parent21cde8b83227fa324f246672b1e2d58408ea6bf8 (diff)
downloadcoreboot-1587dc8a2b4ddfe110cd0239c6506a320cccac96.tar.xz
soc/amd/stoneyridge: Add northbridge support
Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/dimmSpd.c')
-rw-r--r--src/soc/amd/stoneyridge/dimmSpd.c49
1 files changed, 49 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/dimmSpd.c b/src/soc/amd/stoneyridge/dimmSpd.c
new file mode 100644
index 0000000000..80fe12db0c
--- /dev/null
+++ b/src/soc/amd/stoneyridge/dimmSpd.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_def.h>
+#include <device/device.h>
+#include <stdlib.h>
+
+/* warning: Porting.h includes an open #pragma pack(1) */
+#include <Porting.h>
+#include <AGESA.h>
+#include <amdlib.h>
+#include "chip.h"
+#include <dimmSpd.h>
+
+AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
+{
+ int spdAddress;
+ DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ DEVTREE_CONST struct soc_amd_stoneyridge_config *config = dev->chip_info;
+
+ if ((dev == 0) || (config == 0))
+ return AGESA_ERROR;
+ if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
+ return AGESA_ERROR;
+ if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
+ return AGESA_ERROR;
+ if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
+ return AGESA_ERROR;
+ spdAddress = config->spdAddrLookup
+ [info->SocketId] [info->MemChannelId] [info->DimmId];
+ if (spdAddress == 0)
+ return AGESA_ERROR;
+ int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
+ if (err)
+ return AGESA_ERROR;
+ return AGESA_SUCCESS;
+}