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author | Furquan Shaikh <furquan@google.com> | 2018-06-07 15:27:14 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2018-06-07 23:46:01 +0000 |
commit | 1313244ae7537718bfa4fdf1b1155ac9d0ade27c (patch) | |
tree | 9b9095c3a9cbc9f98337008f9fea116b3016e042 /src/soc/amd/stoneyridge/gpio.c | |
parent | 9cd99a1524cd8c7cd6100cfc9d68e85eea5ac265 (diff) | |
download | coreboot-1313244ae7537718bfa4fdf1b1155ac9d0ade27c.tar.xz |
mb/google/octopus: Fix GPIO to GPE mappings in devicetree
Change b41ae2 (mb/google/octopus: Enable wake-over-wifi for octopus
variants) changed the GPE mappings to accomodate for WiFi wake
pin. However, this resulted in TPM interrupt pin being removed from
the GPIO to GPE mapping. Since we do not support true interrupts in
coreboot, GPE_STS registers are used to identify if an interrupt has
triggered. Change in GPE mapping resulted in this information to be
lost when talking to TPM thus resulting in "Timeout wait for tpm
irq".
This change fixes the above issue by assigning GPIO block for TPM
interrupt back to DW1 and moving GPIO block for wake-over-wifi pin to
DW3. DW3 was mapped to NW_31_0 which only has debug header pins and
CNVI pins (none of them are used for reading GPE_STS or as wake
sources).
BUG=b:109824918
TEST=Verified that there are no "Timeout wait for tpm irq" messages
when talking to TPM.
Change-Id: I30768177a838a684948f7485d760c8b83c3190f7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/gpio.c')
0 files changed, 0 insertions, 0 deletions