diff options
author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-05-01 16:14:42 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2019-05-08 13:48:31 +0000 |
commit | 5de4771360c0e57bd76bc81850298091e0b9bde7 (patch) | |
tree | 52d921e282de61c13f662d27165bd7a846414ed8 /src/soc/amd/stoneyridge/gpio.c | |
parent | fe80bf2fd1e4f027d68af1c5bc58a8b1344a806d (diff) | |
download | coreboot-5de4771360c0e57bd76bc81850298091e0b9bde7.tar.xz |
soc/amd/stoneyridge: Rename AcpiMmio blocks
A subsequent patch will move the AcpiMmio support into amd/common.
Take this opportunity to rename the blocks in the 0xfed8xxxx region
with more consistency.
Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/gpio.c')
-rw-r--r-- | src/soc/amd/stoneyridge/gpio.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index da1ba0bb74..b747538eaa 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -228,7 +228,7 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) uint8_t mux, index, gpio; int gevent_num; - inter_master = (uint32_t *)(uintptr_t)(GPIO_CONTROL_MMIO_BASE + inter_master = (uint32_t *)(uintptr_t)(ACPIMMIO_GPIO0_BASE + GPIO_MASTER_SWITCH); direction = 0; edge_level = 0; @@ -252,7 +252,7 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) control = gpio_list_ptr[index].control; control_flags = gpio_list_ptr[index].flags; - mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE); + mux_ptr = (uint8_t *)(uintptr_t)(gpio + ACPIMMIO_IOMUX_BASE); write8(mux_ptr, mux & AMD_GPIO_MUX_MASK); read8(mux_ptr); /* Flush posted write */ /* special case if pin 2 is assigned to wake */ @@ -316,11 +316,13 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) mem_read_write32(inter_master, GPIO_INTERRUPT_EN, GPIO_INTERRUPT_EN); /* Set all SCI trigger direction (high/low) */ - mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_TRIG), + mem_read_write32((uint32_t *) + (uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_TRIG), direction, mask); /* Set all SCI trigger level (edge/level) */ - mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_LEVEL), + mem_read_write32((uint32_t *) + (uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_LEVEL), edge_level, mask); } @@ -348,7 +350,7 @@ static void save_i2c_pin_registers(uint8_t gpio, uint32_t *gpio_ptr; uint8_t *mux_ptr; - mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE); + mux_ptr = (uint8_t *)(uintptr_t)(gpio + ACPIMMIO_IOMUX_BASE); gpio_ptr = (uint32_t *)gpio_get_address(gpio); save_table->mux_value = read8(mux_ptr); save_table->control_value = read32(gpio_ptr); @@ -360,7 +362,7 @@ static void restore_i2c_pin_registers(uint8_t gpio, uint32_t *gpio_ptr; uint8_t *mux_ptr; - mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE); + mux_ptr = (uint8_t *)(uintptr_t)(gpio + ACPIMMIO_IOMUX_BASE); gpio_ptr = (uint32_t *)gpio_get_address(gpio); write8(mux_ptr, save_table->mux_value); read8(mux_ptr); |