soc/amd/stoneyridge: Add I2C devicetree support.

This commit establishes the stoneyridge implementation for i2c entries
in the devicetree.cb file.

BUG=b:72121803

Change-Id: I0d923609bd8fce94c9aee401a5ae2811281b60e5
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 74 insertions, 4 deletions

diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c
index 7ce1c244ca..d3e01090ff 100644
--- a/src/soc/amd/stoneyridge/i2c.c
+++ b/src/soc/amd/stoneyridge/i2c.c
@@ -13,17 +13,87 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <console/console.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <soc/iomap.h>
+#include "chip.h"
+
+#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x))
+#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0))
+#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1))
+#define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2))
+#define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3))
+
+/* Global to provide access to chip.c */
+const char *i2c_acpi_name(const struct device *dev);
 
 static const uintptr_t i2c_bus_address[] = {
-	I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 0,
-	I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 1,
-	I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 2,
-	I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 3,
+	I2CA_BASE_ADDRESS,
+	I2CB_BASE_ADDRESS,
+	I2CC_BASE_ADDRESS,
+	I2CD_BASE_ADDRESS,
 };
 
 uintptr_t dw_i2c_base_address(unsigned int bus)
 {
 	return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0;
 }
+
+const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus,
+		const struct device *dev)
+{
+	const struct soc_amd_stoneyridge_config *config;
+	if (!dev || !dev->chip_info) {
+		printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
+			__func__);
+		return NULL;
+	}
+	if (bus >= ARRAY_SIZE(i2c_bus_address))
+		return NULL;
+
+	config = dev->chip_info;
+	return &config->i2c[bus];
+}
+
+const char *i2c_acpi_name(const struct device *dev)
+{
+	switch (dev->path.mmio.addr) {
+	case I2CA_BASE_ADDRESS:
+		return "I2CA";
+	case I2CB_BASE_ADDRESS:
+		return "I2CB";
+	case I2CC_BASE_ADDRESS:
+		return "I2CC";
+	case I2CD_BASE_ADDRESS:
+		return "I2CD";
+	default:
+		return NULL;
+	}
+}
+
+int dw_i2c_soc_dev_to_bus(struct device *dev)
+{
+	switch (dev->path.mmio.addr) {
+	case I2CA_BASE_ADDRESS:
+		return 0;
+	case I2CB_BASE_ADDRESS:
+		return 1;
+	case I2CC_BASE_ADDRESS:
+		return 2;
+	case I2CD_BASE_ADDRESS:
+		return 3;
+	}
+	return -1;
+}
+
+struct device_operations stoneyridge_i2c_mmio_ops = {
+	/* TODO(teravest): Move I2C resource info here. */
+	.read_resources = DEVICE_NOOP,
+	.set_resources = DEVICE_NOOP,
+	.enable_resources = DEVICE_NOOP,
+	.scan_bus = scan_smbus,
+	.acpi_name = i2c_acpi_name,
+	.acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt,
+};