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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-05-02 17:27:57 -0600
committerMartin Roth <martinroth@google.com>2019-06-06 17:57:40 +0000
commit251d305e73f76ca3b63654273f3b2bb3de775457 (patch)
tree76cf206b9b73033c21569005f12f80f1df7bbcbf /src/soc/amd/stoneyridge/i2c.c
parenteb5b0d05a71ec04d69699edebb6e71be2bb6ed09 (diff)
downloadcoreboot-251d305e73f76ca3b63654273f3b2bb3de775457.tar.xz
soc/amd/stoneyridge: Move GPIO support to common
The banked GPIO functionality in the AcpiMmio block has been consistent since the Mullins product. Move the basic support into a common directory. Each product's pin availability, MUXes, and other details must remain specific to the product. The relocated source also drops the weak configure_gevent_smi() that reports SMI is not available. The stoneyridge port relies on SMI to do its initialization, similar to modern soc/intel devices. This is the plan for future soc/amd ports, so make a missing function a build error instead of a runtime warning. BUG=b:131682806 Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/i2c.c')
-rw-r--r--src/soc/amd/stoneyridge/i2c.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c
index c3e5539e19..7f65a4f3f3 100644
--- a/src/soc/amd/stoneyridge/i2c.c
+++ b/src/soc/amd/stoneyridge/i2c.c
@@ -203,7 +203,7 @@ void sb_reset_i2c_slaves(void)
/* Save and reprogram I2C SCL pins */
for (i = 0; i < saved_pins_count; i++)
save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]);
- sb_program_gpios(i2c_2_gpi, saved_pins_count);
+ program_gpios(i2c_2_gpi, saved_pins_count);
/*
* Toggle SCL back and forth 9 times under 100KHz. A single read is