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authorRaul E Rangel <rrangel@chromium.org>2018-08-02 15:56:34 -0600
committerPatrick Georgi <pgeorgi@google.com>2018-08-06 07:57:12 +0000
commit6b0fc80ff2af15d47ff7e8560768c9ed752594c0 (patch)
treeefac9f5ed321df3341413aecb7ffb6e64db7f5b7 /src/soc/amd/stoneyridge/include
parentc024381f8f1916607a8e5ee209063d17d37a5a61 (diff)
downloadcoreboot-6b0fc80ff2af15d47ff7e8560768c9ed752594c0.tar.xz
soc/amd/stoneyridge: Enable spread spectrum in bootblock
setup_spread_spectrum is called in early_init, meaning the console is not initialized yet. So you won't see boot block booting twice. BUG=b:111610455 TEST=booted grunt and verified that AmdInitReset does not reboot. I had AGESA patched to skip the JTAG check. Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 15c95813ee..64b4b4691d 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -367,6 +367,28 @@
#define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)
#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1
+/* Bit definitions for MISC_MMIO_BASE register MiscClkCntl1 */
+#define MISC_CGPLL_CONFIG1 0x08
+#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)
+#define MISC_CGPLL_CONFIG3 0x10
+#define CG1PLL_REFDIV_SHIFT 0
+#define CG1PLL_REFDIV_MASK (0x3FF << CG1PLL_REFDIV_SHIFT)
+#define CG1PLL_FBDIV_SHIFT 10
+#define CG1PLL_FBDIV_MASK (0xFFF << CG1PLL_FBDIV_SHIFT)
+#define MISC_CGPLL_CONFIG4 0x14
+#define CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT 0
+#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xFFFF << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)
+#define CG1PLL_SS_AMOUNT_DSFRAC_SHIFT 16
+#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xFFFF << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)
+#define MISC_CGPLL_CONFIG5 0x18
+#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT 8
+#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xF << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)
+#define MISC_CGPLL_CONFIG6 0x1C
+#define CG1PLL_LF_MODE_SHIFT 9
+#define CG1PLL_LF_MODE_MASK (0x1FF << CG1PLL_LF_MODE_SHIFT)
+#define MISC_CLK_CNTL1 0x40
+#define CG1PLL_FBDIV_TEST BIT(26)
+
struct stoneyridge_aoac {
int enable;
int status;
@@ -404,6 +426,8 @@ u32 pm_read32(u8 reg);
void pm_write8(u8 reg, u8 value);
void pm_write16(u8 reg, u16 value);
void pm_write32(u8 reg, u32 value);
+u32 misc_read32(u8 reg);
+void misc_write32(u8 reg, u32 value);
uint8_t smi_read8(uint8_t offset);
uint16_t smi_read16(uint8_t offset);
uint32_t smi_read32(uint8_t offset);