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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-11-28 17:51:29 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-19 19:49:19 +0000 |
| commit | a89d19a9800a968c0fe4f3eb4218b9babeefb457 (patch) | |
| tree | c1cb8916dbe1249a985dfd7bafa242a894abed78 /src/soc/amd/stoneyridge/include | |
| parent | d77c764dd1181204b6682b657e561d0a929cf4c7 (diff) | |
| download | coreboot-a89d19a9800a968c0fe4f3eb4218b9babeefb457.tar.xz | |
amd/stoneyridge: Add BIOS RAM R/W functions
The internal FCH contains 256 bytes of "BiosRam" that maintains its
state until RSMRST# is asserted or standby power is lost. Add functions
to support read and write operations.
Change-Id: I2ddf58a63e69b2775de9a8163534b13dad2ea2fe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 73e9b6fcd5..9f91b505c7 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -329,6 +329,12 @@ uint32_t smi_read32(uint8_t offset); void smi_write8(uint8_t offset, uint8_t value); void smi_write16(uint8_t offset, uint16_t value); void smi_write32(uint8_t offset, uint32_t value); +uint8_t biosram_read8(uint8_t offset); +void biosram_write8(uint8_t offset, uint8_t value); +uint16_t biosram_read16(uint8_t offset); +void biosram_write16(uint8_t offset, uint16_t value); +uint32_t biosram_read32(uint8_t offset); +void biosram_write32(uint8_t offset, uint32_t value); uint16_t pm_acpi_pm_cnt_blk(void); uint16_t pm_acpi_pm_evt_blk(void); void xhci_pm_write8(uint8_t reg, uint8_t value); |