diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2019-01-24 11:52:20 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-28 13:35:44 +0000 |
| commit | df3064227fb252ccf0ffac6419910bdd6f6ec536 (patch) | |
| tree | 76eb1e574ff3174611bd338e9abaa54482f5c5be /src/soc/amd/stoneyridge/include | |
| parent | 595202c304d14e17b1ea1514169346d7cc637206 (diff) | |
| download | coreboot-df3064227fb252ccf0ffac6419910bdd6f6ec536.tar.xz | |
amd/stoneyridge: Disable GPIO MASK STATUS
MASK_STATUS disables interrupt status generation for the entire GPIO
controller when any debounce register is configured. This causes
problems when the kernel is loading drivers because we could lose
interrupts for previously loaded devices.
sb_program_gpios is also not setup to wait when configuring
PAD_DEBOUNCE, so there is a potential that we could lose the interrupt
status enable bit for other registers. By disabling MASK_STATUS we avoid
that problem.
BUG=b:113880780
BRANCH=none
TEST=Ran a reboot stress test that concluded that we are no longer
losing TPM interrupts while booting.
Change-Id: Ife1db3b1449f205092509595cbc3eca511bff57a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/gpio.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 47eae84c86..fe8240fb11 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -41,6 +41,10 @@ struct soc_amd_i2c_save { uint8_t mux_value; }; +#define GPIO_MASTER_SWITCH 0xFC +#define GPIO_MASK_STS_EN BIT(28) +#define GPIO_INTERRUPT_EN BIT(30) + #define GPIO_I2C0_SCL BIT(0) #define GPIO_I2C1_SCL BIT(1) #define GPIO_I2C2_SCL BIT(2) |