diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2018-06-28 16:31:45 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-02 07:35:00 +0000 |
| commit | 5b058233882eefc100e4ca49b4bdbedffe395356 (patch) | |
| tree | b42acc09847c2f376e392c5fd270ae37039eb08b /src/soc/amd/stoneyridge/include | |
| parent | 6756c16e82728ce612a333017bf23f5a497f554f (diff) | |
| download | coreboot-5b058233882eefc100e4ca49b4bdbedffe395356.tar.xz | |
stoneyridge: Enable IO CF9 in bootblock
If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or
verstage.
BUG=b:110817463
TEST=built on grunt and made sure that hard_reset() reboots.
Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27267
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 06ef898ca5..9f8a7d2f4b 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -32,6 +32,8 @@ #define PSP_MAILBOX_BAR_EN 0x10 /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PM_DECODE_EN 0x00 +#define CF9_IO_EN BIT(1) #define PM_ISA_CONTROL 0x04 #define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 |