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| author | Marshall Dawson <marshall.dawson@scarletltd.com> | 2018-05-07 09:59:10 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-06-13 21:21:19 +0000 |
| commit | c4be175bdc4ab931547b62b6751865754a614e50 (patch) | |
| tree | a0efa1f25365ad5dae5f3b2f0db3b67b63be4cce /src/soc/amd/stoneyridge/include | |
| parent | c150a57d2989699198358e6066913f7e4dc8abc6 (diff) | |
| download | coreboot-c4be175bdc4ab931547b62b6751865754a614e50.tar.xz | |
amd/stoneyridge: Add early MTRR setup for new callouts
Enable the two ranges to be used for the new callouts, AgesaHeapRebase
and AgesaGetHeapBaseInDram.
TEST=Boot grunt w/experimental blob, try different addresses
BUG=b:74518368
Change-Id: Ic7716794dc7d75f849e6e062865d6efbeb4292df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index bf8ed496ef..3d230c311e 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -25,7 +25,9 @@ * * todo: Revisit this once AGESA no longer programs MTRRs. */ -#define SOC_EARLY_VMTRR_FLASH 2 +#define SOC_EARLY_VMTRR_FLASH 1 +#define SOC_EARLY_VMTRR_CAR_HEAP 2 +#define SOC_EARLY_VMTRR_TEMPRAM 3 void stoney_init_cpus(struct device *dev); |