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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-29 22:31:40 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-31 01:09:18 +0000 |
| commit | ee04881360db7d551cfa49ca80b9b1c21a466439 (patch) | |
| tree | 7347629609311df4724dbb81cfa6389ed93f9994 /src/soc/amd/stoneyridge/include | |
| parent | 5ddcfe5ec17b4b625e7969157a819e931a68d330 (diff) | |
| download | coreboot-ee04881360db7d551cfa49ca80b9b1c21a466439.tar.xz | |
soc/amd/*/psp: move MSR_CU_CBBCFG to common and rename to MSR_PSP_ADDR
TEST=Checked that the MSR is the same for Stoneyridge, Picasso and
Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id15715ed1c17f4fc475985dcb1c31a83713ee65c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 8d8203516c..219af8437a 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -205,8 +205,6 @@ void soc_enable_psp_early(void); #define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ #define PSP_MAILBOX_BAR_EN BIT(4) -#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */ - typedef struct aoac_devs { unsigned int :5; unsigned int ic0e:1; /* 5: I2C0 */ |