soc/amd/stoneyridge: Move I2C bus clear out of gpio.c

Relocate the I2C bus reset code from gpio.c to i2c.c.  When it first
went in, gpio.c was a natural location due to the nature of the
algorithm.  This is preparation for moving most of gpio.c to common
code.

Change-Id: I3b2d8e1b54e7c5929220d763bd99fe01b0636aaa
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32650
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 49 insertions, 26 deletions

diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index fe8240fb11..26d0336d0a 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -36,21 +36,10 @@ struct soc_amd_event {
 	uint8_t event;
 };
 
-struct soc_amd_i2c_save {
-	uint32_t control_value;
-	uint8_t mux_value;
-};
-
 #define GPIO_MASTER_SWITCH	0xFC
 #define   GPIO_MASK_STS_EN	BIT(28)
 #define   GPIO_INTERRUPT_EN	BIT(30)
 
-#define GPIO_I2C0_SCL		BIT(0)
-#define GPIO_I2C1_SCL		BIT(1)
-#define GPIO_I2C2_SCL		BIT(2)
-#define GPIO_I2C3_SCL		BIT(3)
-#define GPIO_I2C_MASK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
-
 #define GPIO_TOTAL_PINS		149
 #define GPIO_PIN_IN		(1 << 0)	/* for byte access */
 #define GPIO_PIN_OUT		(1 << 6)	/* for byte access */
@@ -186,15 +175,6 @@ struct soc_amd_i2c_save {
 #define GPIO_147			147
 #define GPIO_148			148
 
-#define I2C0_SCL_PIN			GPIO_145
-#define I2C1_SCL_PIN			GPIO_147
-#define I2C2_SCL_PIN			GPIO_113
-#define I2C3_SCL_PIN			GPIO_19
-
-#define GPIO_I2C0_ADDRESS		GPIO_BANK2_CONTROL(I2C0_SCL_PIN)
-#define GPIO_I2C1_ADDRESS		GPIO_BANK2_CONTROL(I2C1_SCL_PIN)
-#define GPIO_I2C2_ADDRESS		GPIO_BANK1_CONTROL(I2C2_SCL_PIN)
-#define GPIO_I2C3_ADDRESS		GPIO_BANK0_CONTROL(I2C3_SCL_PIN)
 #define GPIO_SCL_HIGH			0
 #define GPIO_SCL_LOW			GPIO_OUTPUT_ENABLE
 
@@ -373,11 +353,6 @@ struct soc_amd_i2c_save {
 #define GPIO_148_IOMUX_I2C1_SDA 0
 #define GPIO_148_IOMUX_GPIOxx 1
 
-#define I2C0_SCL_PIN_IOMUX_GPIOxx	GPIO_145_IOMUX_GPIOxx
-#define I2C1_SCL_PIN_IOMUX_GPIOxx	GPIO_147_IOMUX_GPIOxx
-#define I2C2_SCL_PIN_IOMUX_GPIOxx	GPIO_113_IOMUX_GPIOxx
-#define I2C3_SCL_PIN_IOMUX_GPIOxx	GPIO_19_IOMUX_GPIOxx
-
 enum {
 	GEVENT_0,
 	GEVENT_1,
@@ -599,7 +574,6 @@ uintptr_t gpio_get_address(gpio_t gpio_num);
  * @return none
  */
 void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size);
-void sb_reset_i2c_slaves(void);
 
 /* Return the interrupt status and clear if set. */
 int gpio_interrupt_status(gpio_t gpio);
diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h
new file mode 100644
index 0000000000..62575d0fb8
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/i2c.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __STONEYRIDGE_I2C_H__
+#define __STONEYRIDGE_I2C_H__
+
+#include <soc/gpio.h>
+
+struct soc_amd_i2c_save {
+	uint32_t control_value;
+	uint8_t mux_value;
+};
+
+#define GPIO_I2C0_SCL			BIT(0)
+#define GPIO_I2C1_SCL			BIT(1)
+#define GPIO_I2C2_SCL			BIT(2)
+#define GPIO_I2C3_SCL			BIT(3)
+#define GPIO_I2C_MASK			(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+#define I2C0_SCL_PIN			GPIO_145
+#define I2C1_SCL_PIN			GPIO_147
+#define I2C2_SCL_PIN			GPIO_113
+#define I2C3_SCL_PIN			GPIO_19
+
+#define GPIO_I2C0_ADDRESS		GPIO_BANK2_CONTROL(I2C0_SCL_PIN)
+#define GPIO_I2C1_ADDRESS		GPIO_BANK2_CONTROL(I2C1_SCL_PIN)
+#define GPIO_I2C2_ADDRESS		GPIO_BANK1_CONTROL(I2C2_SCL_PIN)
+#define GPIO_I2C3_ADDRESS		GPIO_BANK0_CONTROL(I2C3_SCL_PIN)
+
+#define I2C0_SCL_PIN_IOMUX_GPIOxx	GPIO_145_IOMUX_GPIOxx
+#define I2C1_SCL_PIN_IOMUX_GPIOxx	GPIO_147_IOMUX_GPIOxx
+#define I2C2_SCL_PIN_IOMUX_GPIOxx	GPIO_113_IOMUX_GPIOxx
+#define I2C3_SCL_PIN_IOMUX_GPIOxx	GPIO_19_IOMUX_GPIOxx
+
+void sb_reset_i2c_slaves(void);
+
+#endif /* __STONEYRIDGE_I2C_H__ */