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authorMarshall Dawson <marshalldawson3rd@gmail.com>2018-10-05 15:41:03 -0600
committerMartin Roth <martinroth@google.com>2018-10-12 15:13:32 +0000
commitecce847606e18aace9fde5f925a7a3a6a85181ee (patch)
tree897232e4ad2720821e2c429632982c13794d4dde /src/soc/amd/stoneyridge/include
parent10509c6f190c791d4e06006610dd83200c9fad37 (diff)
downloadcoreboot-ecce847606e18aace9fde5f925a7a3a6a85181ee.tar.xz
amd/stoneyridge: Convert hex definitions to lower case
Match the rest of the soc/stoneyridge source. Change-Id: I4531e6dad0362be73499647d9fc93c168b6f163e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h34
1 files changed, 17 insertions, 17 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index e7a8cc32ed..c50733be76 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -232,7 +232,7 @@
#define SPI_CMD_TRIGGER 0x47
#define SPI_CMD_TRIGGER_EXECUTE (BIT(7))
#define SPI_TX_BYTE_COUNT 0x48
-#define SPI_RX_BYTE_COUNT 0x4B
+#define SPI_RX_BYTE_COUNT 0x4b
#define SPI_STATUS 0x4c
#define SPI_DONE_BYTE_COUNT_SHIFT 0
#define SPI_DONE_BYTE_COUNT_MASK 0xff
@@ -280,7 +280,7 @@
#define TOGGLE_ALL_PWR_GOOD BIT(1)
#define XHCI_PM_INDIRECT_INDEX 0x48
-#define XHCI_PM_INDIRECT_DATA 0x4C
+#define XHCI_PM_INDIRECT_DATA 0x4c
#define XHCI_OVER_CURRENT_CONTROL 0x30
#define EHCI_OVER_CURRENT_CONTROL 0x70
@@ -316,15 +316,15 @@
/* FCH AOAC Registers 0xfed81e00 */
#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40
-#define FCH_AOAC_D3_CONTROL_I2C0 0x4A
-#define FCH_AOAC_D3_CONTROL_I2C1 0x4C
-#define FCH_AOAC_D3_CONTROL_I2C2 0x4E
+#define FCH_AOAC_D3_CONTROL_I2C0 0x4a
+#define FCH_AOAC_D3_CONTROL_I2C1 0x4c
+#define FCH_AOAC_D3_CONTROL_I2C2 0x4e
#define FCH_AOAC_D3_CONTROL_I2C3 0x50
#define FCH_AOAC_D3_CONTROL_UART0 0x56
#define FCH_AOAC_D3_CONTROL_UART1 0x58
#define FCH_AOAC_D3_CONTROL_AMBA 0x62
#define FCH_AOAC_D3_CONTROL_USB2 0x64
-#define FCH_AOAC_D3_CONTROL_USB3 0x6E
+#define FCH_AOAC_D3_CONTROL_USB3 0x6e
/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */
#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
#define FCH_AOAC_DEVICE_STATE BIT(2)
@@ -335,15 +335,15 @@
#define FCH_AOAC_IS_SW_CONTROL BIT(7)
#define FCH_AOAC_D3_STATE_CLK_GEN 0x41
-#define FCH_AOAC_D3_STATE_I2C0 0x4B
-#define FCH_AOAC_D3_STATE_I2C1 0x4D
-#define FCH_AOAC_D3_STATE_I2C2 0x4F
+#define FCH_AOAC_D3_STATE_I2C0 0x4b
+#define FCH_AOAC_D3_STATE_I2C1 0x4d
+#define FCH_AOAC_D3_STATE_I2C2 0x4f
#define FCH_AOAC_D3_STATE_I2C3 0x51
#define FCH_AOAC_D3_STATE_UART0 0x57
#define FCH_AOAC_D3_STATE_UART1 0x59
#define FCH_AOAC_D3_STATE_AMBA 0x63
#define FCH_AOAC_D3_STATE_USB2 0x65
-#define FCH_AOAC_D3_STATE_USB3 0x6F
+#define FCH_AOAC_D3_STATE_USB3 0x6f
/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */
#define FCH_AOAC_PWR_RST_STATE BIT(0)
#define FCH_AOAC_RST_CLK_OK_STATE BIT(1)
@@ -373,20 +373,20 @@
#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)
#define MISC_CGPLL_CONFIG3 0x10
#define CG1PLL_REFDIV_SHIFT 0
-#define CG1PLL_REFDIV_MASK (0x3FF << CG1PLL_REFDIV_SHIFT)
+#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT)
#define CG1PLL_FBDIV_SHIFT 10
-#define CG1PLL_FBDIV_MASK (0xFFF << CG1PLL_FBDIV_SHIFT)
+#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT)
#define MISC_CGPLL_CONFIG4 0x14
#define CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT 0
-#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xFFFF << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)
+#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xffff << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)
#define CG1PLL_SS_AMOUNT_DSFRAC_SHIFT 16
-#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xFFFF << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)
+#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xffff << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)
#define MISC_CGPLL_CONFIG5 0x18
#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT 8
-#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xF << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)
-#define MISC_CGPLL_CONFIG6 0x1C
+#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xf << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)
+#define MISC_CGPLL_CONFIG6 0x1c
#define CG1PLL_LF_MODE_SHIFT 9
-#define CG1PLL_LF_MODE_MASK (0x1FF << CG1PLL_LF_MODE_SHIFT)
+#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)
#define MISC_CLK_CNTL1 0x40
#define CG1PLL_FBDIV_TEST BIT(26)