diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2018-06-28 16:31:45 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-02 07:35:20 +0000 |
| commit | 9abc3fe9705764904b6439672cefc859ca3ab278 (patch) | |
| tree | 27d96c72e31fcd846920c1bb57260cf911928f30 /src/soc/amd/stoneyridge/include | |
| parent | 5b058233882eefc100e4ca49b4bdbedffe395356 (diff) | |
| download | coreboot-9abc3fe9705764904b6439672cefc859ca3ab278.tar.xz | |
stoneyridge: Enable legacy IO
Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to
function correctly.
BUG=b:110817463
TEST=ran firmware_CorruptFwSigB on grunt
Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 9f8a7d2f4b..3127f5cd47 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -34,6 +34,7 @@ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PM_DECODE_EN 0x00 #define CF9_IO_EN BIT(1) +#define LEGACY_IO_EN BIT(0) #define PM_ISA_CONTROL 0x04 #define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 |