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| author | Richard Spiegel <richard.spiegel@silverbackltd.com> | 2017-11-08 14:58:30 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-10 19:11:12 +0000 |
| commit | cd04e31c8beaecb2e4c95ab47934b32b2b5e3b06 (patch) | |
| tree | 6c429c36fba38a110f5a85bdab3b28ab784d33a1 /src/soc/amd/stoneyridge/include | |
| parent | 3f6c400310a930d226e85e77f29c51f03578f0f1 (diff) | |
| download | coreboot-cd04e31c8beaecb2e4c95ab47934b32b2b5e3b06.tar.xz | |
soc/amd/stoneyridge: Simplify and fix SMBUS code
Solve issues left from Change-Id Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Unify code: smbus.c to have the actual execution code, sm.c and smbus_spd.c
call functions within smbus.c.
Fix some functions that wrongly use SMBHSTCTRL as the register for the
data being transfered. The correct register is SMBHSTDAT0.
Include file smbus.h should only be used by sm.c, smbus.c and smbus_spd.c.
BUG=b:62200225
Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/smbus.h | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h index db3e9b2e5f..1bb4346186 100644 --- a/src/soc/amd/stoneyridge/include/soc/smbus.h +++ b/src/soc/amd/stoneyridge/include/soc/smbus.h @@ -27,8 +27,10 @@ #define SMBHST_STAT_BUSY 0x01 #define SMBHST_STAT_CLEAR 0xff #define SMBHST_STAT_NOERROR 0x02 +#define SMBHST_STAT_VAL_BITS 0x1f +#define SMBHST_STAT_ERROR_BITS 0x1c -#define SMBSLVSTAT 0x1 +#define SMBSLVSTAT 0x1 #define SMBSLV_STAT_ALERT 0x20 #define SMBSLV_STAT_SHADOW2 0x10 #define SMBSLV_STAT_SHADOW1 0x08 @@ -60,6 +62,9 @@ #define SMBSLVDAT 0xc #define SMBTIMING 0xe +#define SMB_ASF_IO_BASE 0x01 +#define SMB_SPEED_400KHZ (66000000 / (400000 * 4)) + #define AX_INDXC 0 #define AX_INDXP 2 #define AXCFG 4 @@ -86,10 +91,10 @@ #define rcindxp_reg(reg, port, mask, val) \ alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -int do_smbus_recv_byte(u32 smbus_io_base, u32 device); -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); +int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address); +int do_smbus_write_byte(u16 smbus_io_base, u8 device, u8 address, u8 val); +int do_smbus_recv_byte(u16 smbus_io_base, u8 device); +int do_smbus_send_byte(u16 smbus_io_base, u8 device, u8 val); void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val); |