diff options
| author | Patrick Georgi <pgeorgi@google.com> | 2018-10-23 14:35:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-28 13:13:04 +0000 |
| commit | 4fbefc5282916550fe7cdd718263fe4cd957a2f3 (patch) | |
| tree | 401eda723d8c16a545d83c83df4f0e8a6c05cae4 /src/soc/amd/stoneyridge/include | |
| parent | 37d5f004ab5751d2521200df08ef86ce1c3fed47 (diff) | |
| download | coreboot-4fbefc5282916550fe7cdd718263fe4cd957a2f3.tar.xz | |
soc/amd/stoneyridge: Replace public magic numbers
Some "magic" numbers became public available registers/bits after the code
was originally written. Find all magic numbers, and if available in a public
BKDG than replace them with literals.
BUG=b:117648026
TEST=Build and boot grunt.
Change-Id: I96ac59fd92c4a5e27c3836f77bf6633e9b0c4990
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/northbridge.h | 10 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 7f7ac5d750..d62c791b09 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -62,9 +62,15 @@ # define MMIO_RE (1 << 0) #define D18F1_MMIO_LIMIT0_LO 0x84 # define MMIO_NP (1 << 7) +#define D18F1_IO_BASE0_LO 0xc0 +#define D18F1_IO_BASE1_LO 0xc8 +#define D18F1_IO_BASE2_LO 0xd0 +#define D18F1_IO_BASE3_LO 0xd8 +#define D18F1_MMIO_BASE7_LO 0xb8 #define D18F1_MMIO_BASELIM0_HI 0x180 #define D18F1_MMIO_BASE8_LO 0x1a0 #define D18F1_MMIO_LIMIT8_LO 0x1a4 +#define D18F1_MMIO_BASE11_LO 0x1b8 #define D18F1_MMIO_BASELIM8_HI 0x1c0 #define NB_MMIO_BASE_LO(reg) ((reg) * 2 * sizeof(uint32_t) + (((reg) < 8) \ ? D18F1_MMIO_BASE0_LO \ @@ -89,6 +95,10 @@ #define D18F1_VGAEN 0xf4 # define VGA_ADDR_ENABLE (1 << 0) +/* D18F5 */ +#define NB_CAPABILITIES2 0x84 +#define CMP_CAP_MASK 0xff + enum { /* SMM handler area. */ SMM_SUBREGION_HANDLER, diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 681f14922a..cb9c4c6e7c 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -304,6 +304,7 @@ #define LPC_WIDEIO2_GENERIC_PORT 0x90 #define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_RESERVED (BIT(4) | BIT(5)) #define ROUTE_TPM_2_SPI BIT(3) #define SPI_ABORT_ENABLE BIT(2) #define SPI_ROM_ENABLE BIT(1) |