diff options
| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-04-04 10:35:21 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-04-10 17:09:22 +0000 |
| commit | 6d61db0d2cec4a3b141da77bcf5675b8b154c8b7 (patch) | |
| tree | 8e2d52d4603121327fad16fee5f929e80dd35f60 /src/soc/amd/stoneyridge/include | |
| parent | 09a16e6a323e16b0428c4cbd3beae38d394aa91e (diff) | |
| download | coreboot-6d61db0d2cec4a3b141da77bcf5675b8b154c8b7.tar.xz | |
soc/amd/stoneyridege: Create AP jump structure
As part of moving AGESA calls from bootblock to romstage, create
infrastructure to pass a pointer to the AP cores, so they can jump directly
to romstage.
BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.
Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/northbridge.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index d649ada241..92bce98780 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -27,6 +27,26 @@ #define HT_INIT_CONTROL 0x6c # define HTIC_BIOSR_DETECT ((1 << 5) | (1 << 9) | (1 << 10)) +/* NB IOAPIC registers */ +#define NB_IOAPIC_INDEX 0xf8 +#define NB_IOAPIC_DATA 0xfc +#define NB_IOAPIC_FEATURE_CTRL 0x00 +#define NB_IOAPIC_ADDRESS_LOW 0x01 +#define NB_IOAPIC_ADDRESS_HIGH 0x02 +#define NB_IOAPIC_GBIF_IRR 0x0f +#define NB_IOAPIC_BR0_IRR 0x10 +#define NB_IOAPIC_BR1_IRR 0x11 +#define NB_IOAPIC_BR2_IRR 0x12 +#define NB_IOAPIC_BR3_IRR 0x13 +#define NB_IOAPIC_BR4_IRR 0x14 +#define NB_IOAPIC_APG_IRR 0x2f +#define NB_IOAPIC_SPG_IRR 0x30 +#define NB_IOAPIC_SER_IRQ_IRR 0x31 +#define NB_IOAPIC_SCRATCH0 0x3e +#define NB_IOAPIC_SCRATCH1 0x3f + +#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0 + /* D18F1 - Address Map Registers */ /* MMIO base and limit */ @@ -88,5 +108,9 @@ void domain_read_resources(device_t dev); void domain_set_resources(device_t dev); void fam15_finalize(void *chip_info); void setup_uma_memory(void); +uint32_t nb_ioapic_read(unsigned int index); +void nb_ioapic_write(unsigned int index, uint32_t value); +void *get_ap_entry_ptr(void); +void set_ap_entry_ptr(void *entry); #endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */ |