diff options
| author | Daniel Kurtz <djkurtz@chromium.org> | 2019-01-14 14:45:47 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-01-16 18:20:36 +0000 |
| commit | b82afce18aff24b6e5e3b73a67a6533cc4865a26 (patch) | |
| tree | 772e5e50b47e354b7e6ab4e3ef8172dbb0100a96 /src/soc/amd/stoneyridge/include | |
| parent | ac1a5a82181c3276963807c4a11ab5edb5eb52f7 (diff) | |
| download | coreboot-b82afce18aff24b6e5e3b73a67a6533cc4865a26.tar.xz | |
soc/amd/stoneyridge/gpio: Configure debounce for irq gpios
FT4 has a strange property where whenever the debounce registers for any
one gpio are changed, the FT4 disables interrupt propagation for ALL
gpio irqs for ~4ms.
In other words, if an edge interrupt of one gpio happens exactly during
this debounce-irq-off window immediately following the configuration of
another gpio, the interrupt will be lost.
It is quite difficult to deal with this in the kernel, since during kernel
boot time, drivers & devices are probed asynchronously, meaning it may
happen that an already loaded driver may miss an interrupt when some
later driver is being probed and configuring its gpio interrupt.
To eliminate this possibility, we pre-configure the debounce registers in
ram stage for all gpios that will be used as irqs later by the kernel
using the same configuration as used by the kernel, as per this table:
IRQ Debounce
Edge Remove Glitch
Level High Preserve Low Glitch
Level Low Preserve High Glitch
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:113880780
BRANCH=none
TEST=Reboot stress test grunt (>100 times); no messages in dmesg like:
tpm tpm0: Timeout waiting for TPM ready
Change-Id: I94c7ecfb14e5bb209b3598e10287c80eb19da25b
Reviewed-on: https://review.coreboot.org/c/30921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/gpio.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 04eda4934e..422ee57ab3 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -450,9 +450,11 @@ enum { #define INT_SCI_SMI_MASK 0x00f40000 #define IN_GLITCH_SHIFT 5 +#define DEBOUNCE_NONE 0 #define GLITCH_LOW 1 #define GLITCH_HIGH 2 #define GLITCH_NONE 3 +#define GPIO_IN_NO_DEBOUNCE (DEBOUNCE_NONE << IN_GLITCH_SHIFT) #define GPIO_IN_PRESERVE_LOW_GLITCH (GLITCH_LOW << IN_GLITCH_SHIFT) #define GPIO_IN_PRESERVE_HIGH_GLITCH (GLITCH_HIGH << IN_GLITCH_SHIFT) #define GPIO_IN_REMOVE_GLITCH (GLITCH_NONE << IN_GLITCH_SHIFT) |