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| author | Gaggery Tsai <gaggery.tsai@intel.com> | 2018-01-15 15:03:01 +0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2018-02-06 06:14:30 +0000 |
| commit | da6f4ae0b98313aae9e6295e412d87b11199501f (patch) | |
| tree | 1add48cfd2fbb497301c0f1a3f07d495c43849ca /src/soc/amd/stoneyridge/include | |
| parent | c12dff9098fb4023b878102fd5eecdb10c37fcdb (diff) | |
| download | coreboot-da6f4ae0b98313aae9e6295e412d87b11199501f.tar.xz | |
soc/intel/skylake: Set PsysPmax value
According to doc #543977 Power Architecture Guide, PsysPmax is the
maximum platform power. It maps to the full-scale of Psys signal.
This patch adds a "psys_pmax" member in chip information which allows
boards to set up maximum platform power.
BUG=b:71594855
BRANCH=None
TEST=Set "psys_pmax" in device tree & "USE=fw_debug emerge-fizz
chromeos-mrc coreboot chromeos-bootimage" & ensure correct
PsysPmax value is passed to FSP-S through UPD. Verfied on
KBL-R and KBL-U SKUs.
Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
0 files changed, 0 insertions, 0 deletions