diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-10-12 10:38:39 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-14 19:11:34 +0000 |
| commit | ba8751fc722c4636d36331d0cf628d656d2b5cf4 (patch) | |
| tree | cf53d7ed2054d5b03849008475cdd6cd1d28643e /src/soc/amd/stoneyridge/include | |
| parent | c366f90a2e99828f28c39f9d715149cb14af4293 (diff) | |
| download | coreboot-ba8751fc722c4636d36331d0cf628d656d2b5cf4.tar.xz | |
soc/amd/stoneyridge: Rearrange southbridge.h more
Move the SPI base address register definition to D14F3. This was
missed in:
bba043 amd/stoneyridge: Rearrange southbridge.h
Change-Id: Ia722339418c118bdf4b000bbf97ae4266e9b3be2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 896d4948e0..403e980669 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -102,13 +102,6 @@ #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0) -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 -#define ROUTE_TPM_2_SPI BIT(3) -#define SPI_ABORT_ENABLE BIT(2) -#define SPI_ROM_ENABLE BIT(1) -#define SPI_ROM_ALT_ENABLE BIT(0) -#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) - /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 #define GPP_CLK2_REQ_MAP_SHIFT 8 @@ -310,6 +303,13 @@ #define LPC_WIDEIO2_GENERIC_PORT 0x90 +#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ABORT_ENABLE BIT(2) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_ROM_ALT_ENABLE BIT(0) +#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + /* LPC register 0xb8 is DWORD, here there are definitions for byte access. For example, bits 31-24 are accessed through byte access at register 0xbb. */ |