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| author | Chris Ching <chingcodes@google.com> | 2017-10-19 11:45:30 -0600 |
|---|---|---|
| committer | Chris Ching <chingcodes@chromium.org> | 2017-10-19 21:07:10 +0000 |
| commit | 6a35fab2723f3b1ca288cd9224d263570cfbe184 (patch) | |
| tree | 5b07742b8fe915db4d1fddc1af320a670f7ba699 /src/soc/amd/stoneyridge/lpc.c | |
| parent | c5ecd3e14d17c5634247242afc8cd558c1ae158f (diff) | |
| download | coreboot-6a35fab2723f3b1ca288cd9224d263570cfbe184.tar.xz | |
soc/amd/stoneyridge: Use macros for PCI_DEVFN calls
* Change all calls to PCI_DEVFN to macros
* Remove CBB and CDB Kconfig since these are static for stoneyridge
BUG=b:62200746
TEST=build
Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/lpc.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/lpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 8206950a0b..d3cb46fc27 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -44,7 +44,7 @@ static void lpc_init(device_t dev) * Enable the LPC Controller * SMBus register 0x64 is not defined in public datasheet. */ - sm_dev = dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)); + sm_dev = dev_find_slot(0, SMBUS_DEVFN); dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); |