diff options
author | Aaron Durbin <adurbin@chromium.org> | 2018-01-24 17:42:51 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2018-01-25 23:30:14 +0000 |
commit | 51e4c1a76cafa0ddd429ffa78d0e6fdee179f731 (patch) | |
tree | 1c540ebc0ba5a94ed9119b02be2e985597e5c2f9 /src/soc/amd/stoneyridge/monotonic_timer.c | |
parent | f49ddb67de5b6ff86ad080585bd835779521d647 (diff) | |
download | coreboot-51e4c1a76cafa0ddd429ffa78d0e6fdee179f731.tar.xz |
soc/amd/stoneyridge: remove dependence on TSC
The TSC rate is empirically swinging during early boot. That
leaves timestamps and udelay()s to not be correct. To rectify this
stop using TSC for all of these time sources. Instead use the
performance TSC which is at a fixed 100MHz clock. That provides
stable time sources and legit timestamps.
BUG=b:72378235,b:72170796
Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/monotonic_timer.c')
-rw-r--r-- | src/soc/amd/stoneyridge/monotonic_timer.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/monotonic_timer.c b/src/soc/amd/stoneyridge/monotonic_timer.c index 170a640233..7ea571f635 100644 --- a/src/soc/amd/stoneyridge/monotonic_timer.c +++ b/src/soc/amd/stoneyridge/monotonic_timer.c @@ -15,12 +15,18 @@ #include <cpu/x86/msr.h> #include <timer.h> +#include <timestamp.h> #define CU_PTSC_MSR 0xc0010280 #define PTSC_FREQ_MHZ 100 void timer_monotonic_get(struct mono_time *mt) { + mono_time_set_usecs(mt, timestamp_get()); +} + +uint64_t timestamp_get(void) +{ unsigned long long val; msr_t msr; @@ -28,5 +34,5 @@ void timer_monotonic_get(struct mono_time *mt) val = ((unsigned long long)msr.hi << 32) | msr.lo; - mono_time_set_usecs(mt, val / PTSC_FREQ_MHZ); + return val / PTSC_FREQ_MHZ; } |