diff options
author | Marc Jones <marcj303@gmail.com> | 2017-05-15 18:55:11 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-06-26 00:46:18 +0000 |
commit | 1587dc8a2b4ddfe110cd0239c6506a320cccac96 (patch) | |
tree | ab9b3b3ae63461e9fa8caf4c3fe4410f78f664c3 /src/soc/amd/stoneyridge/ramtop.c | |
parent | 21cde8b83227fa324f246672b1e2d58408ea6bf8 (diff) | |
download | coreboot-1587dc8a2b4ddfe110cd0239c6506a320cccac96.tar.xz |
soc/amd/stoneyridge: Add northbridge support
Copy northbridge files from northbridge/amd/pi/00670F00
to soc/amd/stoneyridge and soc/amd/common.
Changes:
- update chip_ops and device_ops
- remove multi-node support
- clean up Kconfig and Makefile
Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/ramtop.c')
-rw-r--r-- | src/soc/amd/stoneyridge/ramtop.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c new file mode 100644 index 0000000000..8fa81c715a --- /dev/null +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <stdint.h> +#include <arch/io.h> +#include <cbmem.h> + +#define CBMEM_TOP_SCRATCHPAD 0x78 + +void backup_top_of_low_cacheable(uintptr_t ramtop) +{ + uint16_t top_cache = ramtop >> 16; + pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache); +} + +uintptr_t restore_top_of_low_cacheable(void) +{ + uint16_t top_cache; + top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD); + return (top_cache << 16); +} |