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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/soc/amd/stoneyridge/ramtop.c | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
| download | coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/ramtop.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/ramtop.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 72db8ec7e1..7439ab41a5 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -19,8 +19,8 @@ #include <stdint.h> #include <arch/io.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> -#include <cpu/amd/amdfam15.h> #include <cbmem.h> #include <stage_cache.h> #include <arch/bert_storage.h> @@ -102,7 +102,7 @@ void smm_region_info(void **start, size_t *size) static void clear_tvalid(void) { msr_t hwcr = rdmsr(HWCR_MSR); - msr_t mask = rdmsr(MSR_SMM_MASK); + msr_t mask = rdmsr(SMM_MASK_MSR); int tvalid = !!(mask.lo & SMM_TSEG_VALID); if (hwcr.lo & SMM_LOCK) { @@ -114,7 +114,7 @@ static void clear_tvalid(void) } mask.lo &= ~SMM_TSEG_VALID; - wrmsr(MSR_SMM_MASK, mask); + wrmsr(SMM_MASK_MSR, mask); } int smm_subregion(int sub, void **start, size_t *size) |