diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-06-15 12:17:38 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-27 20:50:54 +0000 |
| commit | 4e101ada37c10282030729f4a03fd505bd4f526d (patch) | |
| tree | 7cdb6f41b198ef1e9c30f66da854572893de91ed /src/soc/amd/stoneyridge/sata.c | |
| parent | 4692e2fc95605a997cd9cd1cdb711e6c1f6869bc (diff) | |
| download | coreboot-4e101ada37c10282030729f4a03fd505bd4f526d.tar.xz | |
soc/amd/stoneyridge: Fix most checkpatch errors
Correct the majority of reported errors and mark most of the
remaining ones as todo. (Some of the lines requiring a >80
break are indented too much currently.) Some of the alignment
in hudson.h still causes checkpatch errors, but this is
intentionally left as-is.
Also make other misc. changes, e.g. consistency in lower-case
for hex values, using defined values, etc.
These changes were confirmed to cause no changes in a Gardenia
build. No other improvements were made, e.g. changing to helper
functions, or converting functions like __outbyte().
BUG=chrome-os-partner:622407746
Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/sata.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/sata.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index 32090d2963..bd013c895d 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -32,11 +32,11 @@ static void sata_init(struct device *dev) #define AHCI_BASE_ADDRESS_REG 0x24 #define MISC_CONTROL_REG 0x40 #define UNLOCK_BIT (1<<0) - #define SATA_CAPABILITIES_REG 0xFC + #define SATA_CAPABILITIES_REG 0xfc #define CFG_CAP_SPM (1<<12) - volatile u32 *ahci_ptr = - (u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); + volatile u32 *ahci_ptr = (u32 *)(pci_read_config32(dev, + AHCI_BASE_ADDRESS_REG) & 0xffffff00); u32 temp; /* unlock the write-protect */ @@ -45,7 +45,8 @@ static void sata_init(struct device *dev) pci_write_config32(dev, MISC_CONTROL_REG, temp); /* set the SATA AHCI mode to allow port expanders */ - *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM; + *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) + |= CFG_CAP_SPM; /* lock the write-protect */ temp = pci_read_config32(dev, MISC_CONTROL_REG); |