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author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-10-24 12:51:21 -0700 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-30 11:01:37 +0000 |
commit | b40e193948c0af380e9dc19c06a5c93ff8b4f2f0 (patch) | |
tree | 3de92e0841b9ef7e2c2c3a86e6b4cfd404f827dd /src/soc/amd/stoneyridge/smbus_spd.c | |
parent | 9ca43191ab454c777102f9634b5d40478cd4dc58 (diff) | |
download | coreboot-b40e193948c0af380e9dc19c06a5c93ff8b4f2f0.tar.xz |
soc/amd/stoneyridge: Access SMBUS through MMIO
Currently SMBUS registers are accessed through IO, but with stoneyridge
they can be accessed through MMIO. This reduces the time of execution by
a tiny amount (MMIO write is faster than IO write, though MMIO read is about
as fast as IO read) as most of the time consumed is actually transaction
time. Convert code to MMIO access.
BUG=b:117754784
TEST=Used IO to write and MMIO to read, to confirm a one to one relationship
between IO and MMIO. Then build and boot grunt.
Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/smbus_spd.c')
-rw-r--r-- | src/soc/amd/stoneyridge/smbus_spd.c | 30 |
1 files changed, 6 insertions, 24 deletions
diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index 384bc8a391..63b457c2c8 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -27,8 +27,7 @@ * sending offset for every byte. * Reads 128 bytes in 7-8 ms at 400 KHz. */ -static int readspd(uint16_t iobase, uint8_t SmbusSlaveAddress, - char *buffer, size_t count) +static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count) { uint8_t dev_addr; size_t index; @@ -36,8 +35,8 @@ static int readspd(uint16_t iobase, uint8_t SmbusSlaveAddress, char *pbuf = buffer; printk(BIOS_SPEW, "-------------READING SPD-----------\n"); - printk(BIOS_SPEW, "iobase: 0x%08X, SmbusSlave: 0x%08X, count: %d\n", - iobase, SmbusSlaveAddress, (int)count); + printk(BIOS_SPEW, "SmbusSlave: 0x%08X, count: %zd\n", + SmbusSlaveAddress, count); /* * Convert received device address to the format accepted by @@ -46,7 +45,7 @@ static int readspd(uint16_t iobase, uint8_t SmbusSlaveAddress, dev_addr = (SmbusSlaveAddress >> 1); /* Read the first SPD byte */ - error = do_smbus_read_byte(iobase, dev_addr, 0); + error = do_smbus_read_byte(SMBUS_MMIO_BASE, dev_addr, 0); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; @@ -56,7 +55,7 @@ static int readspd(uint16_t iobase, uint8_t SmbusSlaveAddress, /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */ for (index = 1 ; index < count ; index++) { - error = do_smbus_recv_byte(iobase, dev_addr); + error = do_smbus_recv_byte(SMBUS_MMIO_BASE, dev_addr); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; @@ -70,24 +69,7 @@ static int readspd(uint16_t iobase, uint8_t SmbusSlaveAddress, return 0; } -static void write_pm_reg(int reg, int data) -{ - outb(reg, PM_INDEX); - outb(data, PM_DATA); -} - -static void setup_fch(uint16_t ioBase) -{ - write_pm_reg(SMB_ASF_IO_BASE, ioBase >> 8); - outb(SMB_SPEED_400KHZ, ioBase + SMBTIMING); - /* Clear all SMBUS status bits */ - outb(SMBHST_STAT_CLEAR, ioBase + SMBHSTSTAT); - outb(SMBSLV_STAT_CLEAR, ioBase + SMBSLVSTAT); -} - int sb_read_spd(uint8_t spdAddress, char *buf, size_t len) { - uint16_t ioBase = SMB_BASE_ADDR; - setup_fch(ioBase); - return readspd(ioBase, spdAddress, buf, len); + return readspd(spdAddress, buf, len); } |