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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2018-10-24 12:51:21 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-01-30 11:01:37 +0000
commitb40e193948c0af380e9dc19c06a5c93ff8b4f2f0 (patch)
tree3de92e0841b9ef7e2c2c3a86e6b4cfd404f827dd /src/soc/amd/stoneyridge/southbridge.c
parent9ca43191ab454c777102f9634b5d40478cd4dc58 (diff)
downloadcoreboot-b40e193948c0af380e9dc19c06a5c93ff8b4f2f0.tar.xz
soc/amd/stoneyridge: Access SMBUS through MMIO
Currently SMBUS registers are accessed through IO, but with stoneyridge they can be accessed through MMIO. This reduces the time of execution by a tiny amount (MMIO write is faster than IO write, though MMIO read is about as fast as IO read) as most of the time consumed is actually transaction time. Convert code to MMIO access. BUG=b:117754784 TEST=Used IO to write and MMIO to read, to confirm a one to one relationship between IO and MMIO. Then build and boot grunt. Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index eb4188219b..c8d66ac3f2 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -28,6 +28,7 @@
#include <amdblocks/agesawrapper.h>
#include <amdblocks/reset.h>
#include <soc/southbridge.h>
+#include <soc/smbus.h>
#include <soc/smi.h>
#include <soc/amd_pci_int_defs.h>
#include <delay.h>
@@ -619,6 +620,17 @@ static void setup_misc(int *reboot)
}
}
+static void fch_smbus_init(void)
+{
+ pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8);
+ smbus_write8(SMBUS_MMIO_BASE, SMBTIMING, SMB_SPEED_400KHZ);
+ /* Clear all SMBUS status bits */
+ smbus_write8(SMBUS_MMIO_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR);
+ smbus_write8(SMBUS_MMIO_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR);
+ smbus_write8(ASF_MMIO_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR);
+ smbus_write8(ASF_MMIO_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR);
+}
+
/* Before console init */
void bootblock_fch_early_init(void)
{
@@ -631,6 +643,7 @@ void bootblock_fch_early_init(void)
sb_spibase();
sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
sb_acpi_mmio_decode();
+ fch_smbus_init();
sb_enable_cf9_io();
setup_spread_spectrum(&reboot);
setup_misc(&reboot);