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| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-07-26 10:51:38 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-07-31 00:46:07 +0000 |
| commit | 7108107fa2b205ec1cd042923815c6c5342e7ae9 (patch) | |
| tree | 481f0e0aab2406aec526af3d0876fe373896d2df /src/soc/amd/stoneyridge/southbridge.c | |
| parent | 90b2cca81fcb38e2bda94c8715519d1aa4a9d8c1 (diff) | |
| download | coreboot-7108107fa2b205ec1cd042923815c6c5342e7ae9.tar.xz | |
src/soc/amd/stoneyridge: Remove IMC support
Per AMD, the Integrated Micro Controller is not a supported feature of
the Stoney Ridge APU. Systems are expected to implement an external EC
for desired features. Remove all stoney IMC files and functions from
src/soc/amd/stoneyridge.
There are 2 "IMC bits" left (and used) that are not truly IMC. New BKDG
describe these bits, so a new patch will be released later to fix the
names and comment.
BUG=b:111780177
TEST=Build grunt and gardenia
Change-Id: I6a24e4c3f03d04713a030b884c611d9c64c4cb3a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27651
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 18e6c6c59d..63d8806fd0 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -25,10 +25,10 @@ #include <cbmem.h> #include <elog.h> #include <amdblocks/amd_pci_util.h> +#include <amdblocks/agesawrapper.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <soc/amd_pci_int_defs.h> -#include <fchec.h> #include <delay.h> #include <soc/pci_devs.h> #include <agesa_headers.h> @@ -123,12 +123,6 @@ const static struct irq_idx_name irq_association[] = { { PIRQ_PMON, "PerMon" }, { PIRQ_SD, "SD" }, { PIRQ_SDIO, "SDIOt" }, - { PIRQ_IMC0, "IMC INT0" }, - { PIRQ_IMC1, "IMC INT1" }, - { PIRQ_IMC2, "IMC INT2" }, - { PIRQ_IMC3, "IMC INT3" }, - { PIRQ_IMC4, "IMC INT4" }, - { PIRQ_IMC5, "IMC INT5" }, { PIRQ_EHCI, "EHCI" }, { PIRQ_XHCI, "XHCI" }, { PIRQ_SATA, "SATA" }, @@ -766,11 +760,6 @@ void southbridge_final(void *chip_info) { uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; - if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) { - agesawrapper_fchecfancontrolservice(); - if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)) - enable_imc_thermal_zone(); - } if (IS_ENABLED(CONFIG_MAINBOARD_POWER_RESTORE)) restored_power = PM_RESTORE_S0_IF_PREV_S0; pm_write8(PM_RTC_SHADOW, restored_power); |