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authorAaron Durbin <adurbin@chromium.org>2018-01-29 11:45:21 -0700
committerAaron Durbin <adurbin@chromium.org>2018-01-30 05:37:57 +0000
commit063c00c2e00b3457ac336763989a4b254345fb13 (patch)
tree4d50a7a206b65bf7a2df3398aa6b615736d88c68 /src/soc/amd/stoneyridge/spi.c
parent1fcc9f3125f88595a89392e9736ebb01e7788842 (diff)
downloadcoreboot-063c00c2e00b3457ac336763989a4b254345fb13.tar.xz
soc/amd/stoneyridge: utilize full SPI flash controller fifo
The spi flash host controller has a dedicated register for the opcode. Therefore, indicate to the spi subsystem that the opcode size should not be taken into account when determining maximum payload size in spi_crop_chunk(). This allows the full use of the fifo when doing transfers. BUG=b:65485690 Change-Id: Iab27a69ca72fd02bc443f0673983f3b22ffca0f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23492 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/spi.c')
-rw-r--r--src/soc/amd/stoneyridge/spi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c
index 9889727f06..b27d00ca74 100644
--- a/src/soc/amd/stoneyridge/spi.c
+++ b/src/soc/amd/stoneyridge/spi.c
@@ -193,7 +193,7 @@ static const struct spi_ctrlr spi_ctrlr = {
.xfer = spi_ctrlr_xfer,
.xfer_vector = spi_xfer_two_vectors,
.max_xfer_size = SPI_FIFO_DEPTH,
- .flags = SPI_CNTRLR_DEDUCT_CMD_LEN,
+ .flags = SPI_CNTRLR_DEDUCT_CMD_LEN | SPI_CNTRLR_DEDUCT_OPCODE_LEN,
};
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {