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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-05-29 09:24:18 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-06-06 18:50:28 +0000 |
| commit | 6ab5ed3b66fc215d0d03b19ab02fdcf8613c7d09 (patch) | |
| tree | 0a1512a069659f4f16412cb21f5357daa047aa38 /src/soc/amd/stoneyridge/spi.c | |
| parent | eceaa97b27b04a61dd5fb2e68e0f5ac1367a3c0f (diff) | |
| download | coreboot-6ab5ed3b66fc215d0d03b19ab02fdcf8613c7d09.tar.xz | |
soc/amd/stoneyridge: Move LPC support to common
AMD devices traditionally have the LPC-ISA bus at 14.3 and the
definition has been very consistent. Relocate the feature from
stoneyridge into common/block.
BUG=b:131682806
Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/spi.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/spi.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c index c682d980bb..8abfa160f4 100644 --- a/src/soc/amd/stoneyridge/spi.c +++ b/src/soc/amd/stoneyridge/spi.c @@ -26,6 +26,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <soc/southbridge.h> +#include <amdblocks/lpc.h> #include <soc/pci_devs.h> #define SPI_DEBUG_DRIVER CONFIG(DEBUG_SPI_FLASH) @@ -103,11 +104,7 @@ static int execute_command(void) void spi_init(void) { - uintptr_t bar; - - bar = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); - bar = ALIGN_DOWN(bar, 64); - set_spibar(bar); + set_spibar(lpc_get_spibase()); } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, |