diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/soc/amd/stoneyridge/tsc_freq.c | |
parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
download | coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/tsc_freq.c')
-rw-r--r-- | src/soc/amd/stoneyridge/tsc_freq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index a8ed7c6a4c..89b0a7866e 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -17,8 +17,8 @@ #include <arch/io.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include <cpu/x86/tsc.h> -#include <cpu/amd/amdfam15.h> #include <console/console.h> #include <soc/pci_devs.h> #include <device/pci_ops.h> |