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authorMarc Jones <marcj303@gmail.com>2017-05-04 21:17:45 -0600
committerMartin Roth <martinroth@google.com>2017-06-26 00:45:41 +0000
commit244848462def7075e0c812a2f71c408668cacfe4 (patch)
treefde926f45d478b36eaebfd1261886c973b803857 /src/soc/amd/stoneyridge/usb.c
parenta0199d8e1a96d94828b31f77e0a29a282871a76a (diff)
downloadcoreboot-244848462def7075e0c812a2f71c408668cacfe4.tar.xz
soc: Add AMD Stoney Ridge southbridge code
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/usb.c')
-rw-r--r--src/soc/amd/stoneyridge/usb.c56
1 files changed, 56 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c
new file mode 100644
index 0000000000..6f273952cf
--- /dev/null
+++ b/src/soc/amd/stoneyridge/usb.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/pci_ehci.h>
+#include <arch/io.h>
+#include <soc/hudson.h>
+
+static struct pci_operations lops_pci = {
+ .set_subsystem = pci_dev_set_subsystem,
+};
+
+static void usb_init(struct device *dev)
+{
+}
+
+static struct device_operations usb_ops = {
+ .read_resources = pci_ehci_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = usb_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_AMD_SB900_USB_18_0,
+ PCI_DEVICE_ID_AMD_SB900_USB_18_2,
+ PCI_DEVICE_ID_AMD_SB900_USB_20_5,
+ PCI_DEVICE_ID_AMD_CZ_USB_0,
+ PCI_DEVICE_ID_AMD_CZ_USB_1,
+ PCI_DEVICE_ID_AMD_CZ_USB3_0,
+ 0
+};
+
+static const struct pci_driver usb_0_driver __pci_driver = {
+ .ops = &usb_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .devices = pci_device_ids,
+};