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authorMarc Jones <marcj303@gmail.com>2017-11-09 12:25:02 -0700
committerMarc Jones <marc@marcjonesconsulting.com>2017-11-13 17:36:51 +0000
commit290a59284e97498f6cc879ec5638af87d4538b80 (patch)
treefd6ad0732a0475ac789fe3cbb691426140a59f27 /src/soc/amd/stoneyridge
parent31c8cdda73461f59a29457e482934cd686feed39 (diff)
downloadcoreboot-290a59284e97498f6cc879ec5638af87d4538b80.tar.xz
soc/amd/stoneyridge: Add CPU PPKG ASL
Add PPKG Method for processor passive thermal control list. BUG=b:67999819 Change-Id: I5d84832af06f64c923485926e4e0c73c65a2b0b2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22399 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r--src/soc/amd/stoneyridge/acpi/cpu.asl17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl
index 9da1550269..5d29a55089 100644
--- a/src/soc/amd/stoneyridge/acpi/cpu.asl
+++ b/src/soc/amd/stoneyridge/acpi/cpu.asl
@@ -30,3 +30,20 @@ External (\_PR.CP04, DeviceObj)
External (\_PR.CP05, DeviceObj)
External (\_PR.CP06, DeviceObj)
External (\_PR.CP07, DeviceObj)
+
+/* Return a package containing enabled processor entries */
+Method (PPKG)
+{
+ If (LGreaterEqual (\PCNT, 2)) {
+ Return (Package ()
+ {
+ \_PR.CP00,
+ \_PR.CP01
+ })
+ } Else {
+ Return (Package ()
+ {
+ \_PR.CP00
+ })
+ }
+}