diff options
author | Marc Jones <marcj303@gmail.com> | 2017-12-01 17:17:43 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-12-06 16:23:33 +0000 |
commit | 7654f86f3ab5ad87b7a224b075842a35b8b8748b (patch) | |
tree | 6cc7f96e14256fa1a2d33a601375713b510a62ab /src/soc/amd/stoneyridge | |
parent | 2bd52ff0bd0c3837db7a3b5d26539d1b90036f2f (diff) | |
download | coreboot-7654f86f3ab5ad87b7a224b075842a35b8b8748b.tar.xz |
soc/amd/stoneyridge: Add XHCI PM register access functions
Add functions to access the XHCI PM MMIO registers.
Change-Id: I81b4c0a448eb17c5ee0562a2c3548a074d533a98
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r-- | src/soc/amd/stoneyridge/include/soc/iomap.h | 1 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 6 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/sb_util.c | 30 |
3 files changed, 37 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 53eb7120ae..64a9b30f2f 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -31,6 +31,7 @@ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 #define APU_SMI_BASE 0xfed80200 #define PM_MMIO_BASE 0xfed80300 +#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00 #define APU_UART0_BASE 0xfedc6000 #define APU_UART1_BASE 0xfedc8000 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index d9114728e3..f840fd9296 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -312,6 +312,12 @@ void smi_write16(uint8_t offset, uint16_t value); void smi_write32(uint8_t offset, uint32_t value); uint16_t pm_acpi_pm_cnt_blk(void); uint16_t pm_acpi_pm_evt_blk(void); +void xhci_pm_write8(uint8_t reg, uint8_t value); +uint8_t xhci_pm_read8(uint8_t reg); +void xhci_pm_write16(uint8_t reg, uint16_t value); +uint16_t xhci_pm_read16(uint8_t reg); +void xhci_pm_write32(uint8_t reg, uint32_t value); +uint32_t xhci_pm_read32(uint8_t reg); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); void bootblock_fch_early_init(void); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index f7c6b45ac3..8862b1710b 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -84,3 +84,33 @@ uint16_t pm_acpi_pm_evt_blk(void) { return pm_read16(PM_EVT_BLK); } + +void xhci_pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); +} + +uint8_t xhci_pm_read8(uint8_t reg) +{ + return read8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); +} + +void xhci_pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); +} + +uint16_t xhci_pm_read16(uint8_t reg) +{ + return read16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); +} + +void xhci_pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); +} + +uint32_t xhci_pm_read32(uint8_t reg) +{ + return read32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); +} |