diff options
author | Marc Jones <marcj303@gmail.com> | 2017-10-05 21:56:15 -0600 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-20 21:32:16 +0000 |
commit | 2e8476c35dc5d319af67c16bc24e7b1776f5d63c (patch) | |
tree | eedab1775847e5b47189dc6ff9f64f769afd055d /src/soc/amd/stoneyridge | |
parent | c866f878bc51151b5a0934544e2e066e3ebef234 (diff) | |
download | coreboot-2e8476c35dc5d319af67c16bc24e7b1776f5d63c.tar.xz |
stoneyridge: Fix USB ASL
Stoney Ridge has one EHCI controller and one XHCI controller.
Also, update the Kahlee and Gardenia mainboards ASL to match.
Change-Id: I5749ca0640796732e74e551147f8c4446317b77e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r-- | src/soc/amd/stoneyridge/acpi/usb.asl | 35 |
1 files changed, 3 insertions, 32 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl index 30fac2aea9..b93555a2ed 100644 --- a/src/soc/amd/stoneyridge/acpi/usb.asl +++ b/src/soc/amd/stoneyridge/acpi/usb.asl @@ -14,41 +14,12 @@ * GNU General Public License for more details. */ -/* 0:12.0 - OHCI */ -Device(UOH1) { +/* 0:12.0 - EHCI */ +Device(EHC0) { Name(_ADR, 0x00120000) Name(_PRW, Package() {0x0b, 3}) -} /* end UOH1 */ +} /* end EHC0 */ -/* 0:12.2 - EHCI */ -Device(UOH2) { - Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0b, 3}) -} /* end UOH2 */ - -/* 0:13.0 - OHCI */ -Device(UOH3) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0b, 3}) -} /* end UOH3 */ - -/* 0:13.2 - EHCI */ -Device(UOH4) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0b, 3}) -} /* end UOH4 */ - -/* 0:16.0 - OHCI */ -Device(UOH5) { - Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0b, 3}) -} /* end UOH5 */ - -/* 0:16.2 - EHCI */ -Device(UOH6) { - Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0b, 3}) -} /* end UOH5 */ /* 0:10.0 - XHCI 0*/ Device(XHC0) { |