diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-05-31 09:21:07 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-03 17:44:04 +0000 |
| commit | 79e12abb1bdf9e25e23d6b7313f087fae81e5a60 (patch) | |
| tree | d08f732b47d1f75808313441e8f8ac14e31eff40 /src/soc/amd/stoneyridge | |
| parent | 0ef6562656acd04125fb2b8484d44277f173b1b0 (diff) | |
| download | coreboot-79e12abb1bdf9e25e23d6b7313f087fae81e5a60.tar.xz | |
soc/amd: Use mp_cpu_bus_init()
Change-Id: Ia4508a9a087e3996ef7667280f8e2788421e5700
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/cpu.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/cpu.h | 3 |
3 files changed, 3 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 41fcafbab9..909b84793e 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -25,7 +25,7 @@ extern const char *i2c_acpi_name(const struct device *dev); struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = stoney_init_cpus, + .init = mp_cpu_bus_init, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 36583a50ea..9189cfb8c1 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -93,10 +93,10 @@ static const struct mp_ops mp_ops = { .post_mp_init = enable_smi_generation, }; -void stoney_init_cpus(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + if (mp_init_with_smm(cpu_bus, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); /* The flash is now no longer cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index ea51f76a3e..8d25fb6d4e 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -3,8 +3,6 @@ #ifndef __STONEYRIDGE_CPU_H__ #define __STONEYRIDGE_CPU_H__ -#include <device/device.h> - /* * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest * numbered registers. Any values defined below are subtracted from the @@ -16,7 +14,6 @@ #define SOC_EARLY_VMTRR_CAR_HEAP 2 #define SOC_EARLY_VMTRR_TEMPRAM 3 -void stoney_init_cpus(struct device *dev); void check_mca(void); #endif /* __STONEYRIDGE_CPU_H__ */ |