diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-04-09 22:15:06 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-04-11 14:13:56 +0000 |
| commit | 8f031d8234212266a6a18747415550ae5b89c776 (patch) | |
| tree | 3d26310924fa9ee472e5fb9a7fd1adfbe29fb4fa /src/soc/amd/stoneyridge | |
| parent | fbc66b9dc035bcd287d434363ce984c41118bf95 (diff) | |
| download | coreboot-8f031d8234212266a6a18747415550ae5b89c776.tar.xz | |
amd/stoneyridge: Reorder temp mtrr for flash
Relocate setting the temp range MTRR, for the SPI flash device, to
after completion of mp_init. The mp_init functionality mirrors the
BSP's exact MTRR settings into the AP cores. The ranges need to be
the correct calculated values and not some temporary setting.
This solves an MTRR sync issue on APUs with more than two cores,
i.e. more than a single compute-unit. MTRRs within a CU are shared
so the AP always stays in sync.
BUG=b:77457944
TEST=run on Kahlee
Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/cpu.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 14b6881a1a..15dd38147c 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -49,10 +49,6 @@ static struct smm_relocation_attrs relo_attrs; static void pre_mp_init(void) { x86_setup_mtrrs_with_detect(); - - /* The flash is now no longer cacheable. Reset to WP for performance. */ - mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - x86_mtrr_check(); } @@ -113,6 +109,9 @@ void stoney_init_cpus(struct device *dev) /* Clear for take-off */ if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); + + /* The flash is now no longer cacheable. Reset to WP for performance. */ + mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); } static void model_15_init(device_t dev) |