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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-09-26 16:07:59 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-01 14:51:17 +0000 |
| commit | 9c5dc1fd449331a16b6cc50afba83e41aa20185e (patch) | |
| tree | b59d35aac3a41b68a6a00051ae469caf19dbb4f0 /src/soc/amd/stoneyridge | |
| parent | 14331fdae611fcba169552d1d6e29c5015399bf9 (diff) | |
| download | coreboot-9c5dc1fd449331a16b6cc50afba83e41aa20185e.tar.xz | |
amd/stoneyridge: Add FCH WAK and PTS methods
Add methods that can be used for preparing all controller hub devices
for sleep, and that will turn the devices back on.
BUG=b:77602074
Change-Id: I4b0c48e96aff23b4c31c9e89582b9fa80dba7bda
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28770
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 2271d67d00..b8956b4984 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -581,3 +581,61 @@ Method(FDDC, 2, Serialized) } Release(FDAS) } + +Method(FPTS,0, Serialized) /* FCH _PTS */ +{ + if(LEqual(\XHCE, one)) { + if(LNotEqual(U3TD, 0x03)) { + FDDC(23, 3) + } + } + if(LNotEqual(U2TD, 0x03)) { + FDDC(18, 3) + } + + if(LNotEqual(SATD, 0x00)) { + FDDC(15, 0) /* wake SATA before sleep */ + } +} + +Method(FWAK,0, Serialized) /* FCH _WAK */ +{ + if(LEqual(\XHCE, one)) { + if(LEqual(U3TD, 0x03)) { + FDDC(23, 0) + } + } + if(LEqual(U2TD, 0x03)) { + FDDC(18, 0) + } + if(LEqual(\UT0E, zero)) { + if(LNotEqual(U0TD, 0x03)) { + FDDC(11, 3) + } + } + if(LEqual(\UT1E, zero)) { + if(LNotEqual(U1TD, 0x03)) { + FDDC(12, 3) + } + } + if(LEqual(\IC0E, zero)) { + if(LNotEqual(I0TD, 0x03)) { + FDDC(5, 3) + } + } + if(LEqual(\IC1E, zero)) { + if(LNotEqual(I1TD, 0x03)) { + FDDC(6, 3) + } + } + if(LEqual(\IC2E, zero)) { + if(LNotEqual(I2TD, 0x03)) { + FDDC(7, 3) + } + } + if(LEqual(\IC3E, zero)) { + if(LNotEqual(I3TD, 0x03)) { + FDDC(8, 3) + } + } +} |