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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-12-14 10:00:27 -0700
committerMartin Roth <martinroth@google.com>2017-12-18 16:52:27 +0000
commit2942db6d6d7248fb4f2a61970b7048e2c7aa8b6c (patch)
tree09d340d7f2e385ac60cfa7bff71e25cd4cf1ded7 /src/soc/amd/stoneyridge
parentff4da93f4e2a5279622b3669b845139f02adc166 (diff)
downloadcoreboot-2942db6d6d7248fb4f2a61970b7048e2c7aa8b6c.tar.xz
soc/amd: Move stoneyridge features out of agesawrapper
The AGESA wrapper should not use and CONFIG_STONEY* values, nor should it make any assumptions about the capabilities of a particular device. Move these into stoneyridge northbridge and southbridge files. BUG=b:70670425 TEST=Build and run Kahlee Change-Id: I706edbb6a048b64389ba3077d5df0fe6155070b3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r--src/soc/amd/stoneyridge/northbridge.c14
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c28
2 files changed, 42 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 90ece8e014..9d2823f329 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -30,9 +30,11 @@
#include <device/pci_ids.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/agesawrapper_call.h>
+#include <agesa_headers.h>
#include <soc/northbridge.h>
#include <soc/southbridge.h>
#include <soc/pci_devs.h>
+#include <soc/iomap.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
@@ -556,3 +558,15 @@ u32 map_oprom_vendev(u32 vendev)
return new_vendev;
}
+
+void SetNbEnvParams(GNB_ENV_CONFIGURATION *params)
+{
+ params->IommuSupport = FALSE;
+}
+
+void SetNbMidParams(GNB_MID_CONFIGURATION *params)
+{
+ /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */
+ params->iGpuVgaMode = 0;
+ params->GnbIoapicAddress = IO_APIC2_ADDR;
+}
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index a9081f87e0..1357257ea9 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -31,6 +31,34 @@
#include <fchec.h>
#include <delay.h>
#include <soc/pci_devs.h>
+#include <agesa_headers.h>
+
+static int is_sata_config(void)
+{
+ return !((CONFIG_STONEYRIDGE_SATA_MODE == SataNativeIde)
+ || (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde));
+}
+
+void SetFchResetParams(FCH_RESET_INTERFACE *params)
+{
+ params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE);
+ params->SataEnable = is_sata_config();
+ params->IdeEnable = !params->SataEnable;
+}
+
+void SetFchEnvParams(FCH_INTERFACE *params)
+{
+ params->AzaliaController = AzEnable;
+ params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
+ params->SataEnable = is_sata_config();
+ params->IdeEnable = !params->SataEnable;
+ params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde);
+}
+
+void SetFchMidParams(FCH_INTERFACE *params)
+{
+ SetFchEnvParams(params);
+}
/*
* Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME