diff options
author | Martin Roth <martinroth@google.com> | 2017-10-02 13:46:50 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-10-20 17:48:37 +0000 |
commit | c450fbe909e7ed1bc8309ace60ad45fc65a208e1 (patch) | |
tree | 0cc2ab84880902aa015517776b43c0fa5bec7368 /src/soc/amd/stoneyridge | |
parent | 44aaf6137d0e000d6a83ca036aad5722b485d716 (diff) | |
download | coreboot-c450fbe909e7ed1bc8309ace60ad45fc65a208e1.tar.xz |
Stoney Ridge Platforms: Make AGESA callout tables common
There was no reason to have the AGESA callout tables in each mainboard,
so move them to soc/amd/common.
Move chip specific functions into the stoneyridge directory:
- agesa_fch_initreset
- agesa_fch_initenv
- agesa_ReadSpd
Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which
to use.
Soldered-down memory still needs to be supported in a future commit, as
stoney supports both DDR3 & DDR4. A bug has been filed for support for
the upcoming Grunt platform.
BUG=b:67209686
TEST=Build and boot on Kahlee
Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r-- | src/soc/amd/stoneyridge/BiosCallOuts.c | 115 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/Makefile.inc | 3 |
2 files changed, 118 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c new file mode 100644 index 0000000000..0686880ca2 --- /dev/null +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <BiosCallOuts.h> +#include <soc/southbridge.h> + +#include <agesawrapper.h> +#include <AGESA.h> +#include <amdlib.h> +#include <dimmSpd.h> + +AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; + + if (StdHeader->Func == AMD_INIT_RESET) { + FCH_RESET_DATA_BLOCK *FchParams_reset; + FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + FchParams_reset->FchReset.SataEnable = sb_sata_enable(); + FchParams_reset->FchReset.IdeEnable = sb_ide_enable(); + + /* Get platform specific configuration changes */ + platform_FchParams_reset(FchParams_reset); + + printk(BIOS_DEBUG, "Done\n"); + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; + + if (StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) + oem_fan_control(FchParams_env); + + /* XHCI configuration */ + if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE)) + FchParams_env->Usb.Xhci0Enable = TRUE; + else + FchParams_env->Usb.Xhci0Enable = FALSE; + FchParams_env->Usb.Xhci1Enable = FALSE; + + /* 8: If USB3 port is unremoveable. */ + FchParams_env->Usb.USB30PortInit = 8; + + /* SATA configuration */ + FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; + switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams_env->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams_env->Sata.SataIdeMode = TRUE; + break; + } + + /* Platform updates */ + platform_FchParams_env(FchParams_env); + + printk(BIOS_DEBUG, "Done\n"); + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesa_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status = AGESA_UNSUPPORTED; + + if (!ENV_ROMSTAGE) + return Status; + + if (IS_ENABLED(CONFIG_GENERIC_SPD_BIN)) { + AGESA_READ_SPD_PARAMS *info = ConfigPtr; + if (info->MemChannelId > 0) + return AGESA_UNSUPPORTED; + if (info->SocketId != 0) + return AGESA_UNSUPPORTED; + if (info->DimmId > 1) + return AGESA_UNSUPPORTED; + + die("SPD in cbfs not yet supported.\n"); + } else { + Status = AmdMemoryReadSPD(Func, Data, ConfigPtr); + } + + return Status; +} diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index d11fac1659..78ece2ef91 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -38,12 +38,14 @@ subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c +bootblock-y += BiosCallOuts.c bootblock-y += fixme.c bootblock-y += bootblock/bootblock.c bootblock-y += early_setup.c bootblock-y += pmutil.c bootblock-y += tsc_freq.c +romstage-y += BiosCallOuts.c romstage-y += romstage.c romstage-y += early_setup.c romstage-y += dimmSpd.c @@ -66,6 +68,7 @@ verstage-y += tsc_freq.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c postcar-y += ramtop.c +ramstage-y += BiosCallOuts.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c |