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authorNico Huber <nico.h@gmx.de>2018-10-06 18:20:47 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-22 08:34:56 +0000
commit73c11194b0ea6a4fb93456fdff36cbd91838d4ec (patch)
tree0ac3c3429f443cd7d0f708a8b33706a1996d43fc /src/soc/amd/stoneyridge
parent8ba7023cf87413256bfc9c0902d9e69300e91a0b (diff)
downloadcoreboot-73c11194b0ea6a4fb93456fdff36cbd91838d4ec.tar.xz
soc/amd: Implement common reset API
Add an `amdblocks` internal API and rename soft_reset() => warm_reset() hard_reset() => cold_reset() as these terms are commonly used in the surrounding code. On Stoney Ridge, make board_reset() call cold_reset() to keep current behaviour of common code calling hard_reset(). But add a TODO if this is intended. Note: Stoney Ridge is using CF9 for the actual reset but the configuration for a cold reset doesn't use the usual full reset bit but some other mechanism. Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r--src/soc/amd/stoneyridge/Kconfig1
-rw-r--r--src/soc/amd/stoneyridge/reset.c11
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c4
3 files changed, 11 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 1f2331a07d..4411984d80 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -39,7 +39,6 @@ config CPU_SPECIFIC_OPTIONS
select GENERIC_UDELAY
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
- select HAVE_HARD_RESET
select HAVE_MONOTONIC_TIMER
select SPI_FLASH if HAVE_ACPI_RESUME
select TSC_SYNC_LFENCE
diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c
index 738ec59354..34aa576a09 100644
--- a/src/soc/amd/stoneyridge/reset.c
+++ b/src/soc/amd/stoneyridge/reset.c
@@ -20,6 +20,7 @@
#include <soc/pci_devs.h>
#include <device/pci_ops.h>
#include <soc/southbridge.h>
+#include <amdblocks/reset.h>
void set_warm_reset_flag(void)
{
@@ -45,7 +46,7 @@ static void clear_bios_reset(void)
pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
}
-void do_hard_reset(void)
+void do_cold_reset(void)
{
clear_bios_reset();
@@ -55,7 +56,7 @@ void do_hard_reset(void)
outb(RST_CMD | SYS_RST, SYS_RESET);
}
-void do_soft_reset(void)
+void do_warm_reset(void)
{
set_warm_reset_flag();
clear_bios_reset();
@@ -63,3 +64,9 @@ void do_soft_reset(void)
/* Assert reset signals only. */
outb(RST_CMD | SYS_RST, SYS_RESET);
}
+
+void do_board_reset(void)
+{
+ /* TODO: Would a warm_reset() suffice? */
+ do_cold_reset();
+}
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 37ebdc115d..326ea613b0 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -26,6 +26,7 @@
#include <elog.h>
#include <amdblocks/amd_pci_util.h>
#include <amdblocks/agesawrapper.h>
+#include <amdblocks/reset.h>
#include <soc/southbridge.h>
#include <soc/smi.h>
#include <soc/amd_pci_int_defs.h>
@@ -33,7 +34,6 @@
#include <soc/pci_devs.h>
#include <agesa_headers.h>
#include <soc/nvs.h>
-#include <reset.h>
/*
* Table of devices that need their AOAC registers enabled and waited
@@ -639,7 +639,7 @@ void bootblock_fch_early_init(void)
setup_misc(&reboot);
if (reboot)
- soft_reset();
+ warm_reset();
sb_enable_legacy_io();
enable_aoac_devices();