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authorFurquan Shaikh <furquan@google.com>2020-04-27 15:41:35 -0700
committerFurquan Shaikh <furquan@google.com>2020-04-28 22:56:51 +0000
commit088b9e337cfa0bce05ddbdbc643c29676e842f8f (patch)
treeb10df42f75fb7379b593f398554da758a671af7d /src/soc/amd/stoneyridge
parent69c0469bb94662f0fff523fe6eeb84911b397a47 (diff)
downloadcoreboot-088b9e337cfa0bce05ddbdbc643c29676e842f8f.tar.xz
soc/amd/sata: Move SATA PCI device from DSDT to SSDT
This change adds support in common block SATA driver to add a PCI device for SATA in SSDT and removes the SATA device from DSDT. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769 Change-Id: I16ac36d997496ff33c5b44ec9bd2731b2b8799eb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40769 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r--src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
index 8cf8da4e24..cfd2f1df7b 100644
--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
@@ -23,11 +23,6 @@ Method(_OSC,4)
/* Describe the Southbridge devices */
-/* 0:11.0 - SATA */
-Device(STCR) {
- Name(_ADR, 0x00110000)
-} /* end STCR */
-
/* 0:14.0 - SMBUS */
Device(SBUS) {
Name(_ADR, 0x00140000)